The present invention relates to a data reproduction method, and a circuit therefor, for use in a digital magnetic recording/reproduction apparatus, and more particularly, to a data reproduction method, and a circuit therefor, for faithfully reproducing digital data from a recording medium by removing a glitch error which may occur when the digital data recorded on the recording medium is recovered, before the recovered digital data is synchronized with a reproduced clock.
FIG. 1 is a block diagram showing a conventional data reproduction circuit in a digital magnetic recording/reproduction apparatus. As shown in FIG. 1, digital data which is reproduced from a recording medium via a reproducing head (not shown) is amplified to a predetermined level by a reproduction amplifier 1 and is then applied to a reproduction equalizer 2. Reproduction equalizer 2 corrects the waveform output by the reproduction amplifier 1 so as to easily convert the output signal from reproduction amplifier 1 (i.e., a reproduced digital data signal closely related to an analog signal) into the original digital data, and then outputs the result to a data detector 3.
Data detector 3 recovers the reproduced digital data from the output signal of reproduction equalizer 2 and then outputs the recovered digital data to a data/clock synchronizer 5. A reproduced clock recovery portion 4 recovers a reproduced clock from the output signal of reproduction equalizer 2 and then outputs the recovered clock to data/clock synchronizer 5. Data/clock synchronizer 5 synchronizes the reproduced digital data with the reproduced clock and then outputs the result.
Generally, when the digital data recorded on a magnetic recording medium is reproduced by a digital magnetic recording/reproduction apparatus, the reproduced digital data has analog signal characteristics due to the analog-like characteristics and differentiation characteristics of the magnetic recording medium itself.
However, when the reproduced digital data having analog characteristics is recovered into the original digital data by the conventional data reproduction circuit, an undesired component may occur due to the external noise or the excessive high frequency band emphasis characteristic of the reproduction equalizer. The undesired component, i.e., the glitch, is shown in the form of sharp digital data which is much shorter than a minimum run length determined by the highest frequency component among the detected digital data. Here, problems which may occur when the digital data including the glitch component is synchronized with the reproduced clock without elimination of the glitch component are shown in FIGS. 2A to 2C.
As shown in FIGS. 2A to 2C, it is assumed that the data are synchronized with the clock at a rising edge of the reproduced clock (see FIG. 2A). That is, the data status at the current rising edge of the reproduced clock (see FIG. 2A) is continuously maintained at the next rising edge. As shown in FIG. 2B, glitches #1 and #3 are not detected as errors because they do not overlap the rising edges of the reproduced clock shown in FIG. 2A. However, glitches #2 and #4 overlap the rising edges of the reproduced clock (see FIG. 2A), and are therefore detected as errors at the output (see FIG. 2C) of data/clock synchronizer 5.